Synthesis of a Multichannel Conflict-free Data-Exchange Device for Mobile Robotic Platforms
DOI:
https://doi.org/10.47839/ijc.25.2.4653Keywords:
mobile robotic platforms, conflict-free data-exchange methods, multi-port memory, controller, multichannel device, transceiver, interfaceAbstract
This article addresses the enhancement of time-division multiple-access (TDMA) for multi-port memory access, the development of a synthesis method for conflict-free multichannel data-exchange devices, and VLSI-oriented component structures. Methods of conflict-free exchange for groups of mobile robotic platforms were analyzed. TDMA was selected for inter-device exchange and was improved by pipelining the memory-access process. The study proposed a multi-port memory controller structure that was targeted at VLSI implementation, interoperates with heterogeneous peripherals and memories, employs a pipelined access path, and synchronizes asynchronously operating devices on the memory bus. A reusable base structure was introduced to shorten synthesis time for parameterized multichannel devices. A configurable clock-generation block was designed to match memory throughput and device count, alongside interface-adaptation blocks were created to bridge transceivers and the controller. A method for synthesizing a multichannel device for conflict-free data exchange has been developed, which ensures the coordination of the intensity of data arrival with the bandwidth of the multiport memory. Modeling of the multiport memory controller on the Cyclone III EP3C16F484C6 FPGA showed that its implementation requires only 114 logic elements and 63 registers. The proposed pipeline of the memory access process allowed to reduce the access cycle time to a value close to the register access time, and the use of a parametric basic structure reduced the complexity of the synthesis of multichannel devices by 58–79%.
References
I.G. Tsmots, Yu.V. Opotiak, K.M. Obelovska, S.V. Tesliuk, “Methods and means of conflict-free data exchange in the group of mobile robotic platforms,” Ukrainian Journal of Information Technology, vol. 6, no. 1, pp. 65–75, 2024. https://doi.org/10.23939/ujit2024.01.065.
I. Tsmots, V. Teslyuk, A. Łukaszewicz, Y. Lukashchuk, I. Kazymyra, A. Holovatyy, Y. Opotyak, “An approach to the implementation of a neural network for cryptographic protection of data transmission at UAV,” Drones, vol. 7, p. 507, 2023. https://doi.org/10.3390/drones7080507.
D.S. Ilcev, “Analyses of time division multiple access (TDMA) schemes for global mobile satellite communications (GMSC),” TransNav, vol. 14, no. 4, pp. 831–837, 2020. https://doi.org/10.12716/1001.14.04.06.
S.D. Ilcev, “Analyses of space division multiple access (SDMA) schemes for global mobile satellite communications (GMSC),” TransNav, vol. 14, no. 4, 2020. https://doi.org/10.12716/1001.14.04.05.
S.D. Ilcev, “Analyses of code division multiple access (CDMA) schemes for global mobile satellite communications (GMSC),” TransNav, vol. 14, no. 4, 2020. https://doi.org/10.12716/1001.14.04.03.
Telecomunicazioni, “TDMA, FDMA, and CDMA,” University of Rome La Sapienza, Rome, Italy, 2008, 42 p.
G. Garvey, Multiple Access Techniques, Atlanta RF, LLC, Roswell, GA, 2013, 53 p.
X. Xu et al., “Combination of asymmetric PCMA and common multiple access technology,” in Proc. Int. Conf. (TLICSC), 2018, pp. 1–9. https://doi.org/10.2991/tlicsc-18.2018.36.
W. Wolf, Modern VLSI Design: IP-Based Design, 4th ed., Upper Saddle River, NJ: Prentice Hall, 2006.
J.-L. Lin, B.-C.C. Lai, “BRAM-efficient multiported memory on FPGA” Proc. Int. Symp. VLSI Design, Automation and Test (VLSI-DAT), Apr. 2015, pp. 1–4. https://doi.org/10.1109/VLSI-DAT.2015.7114526.
A. Pandey, B. Suhas A, B.P. and S. Madhavan, “Design and implementation of synchronous dual-port memory,” Proceedings of the 2024 Third Int. Conf. on Distributed Computing and Electrical Circuits and Electronics (ICDCECE), Ballari, India, 2024, pp. 1–6. https://doi.org/10.1109/ICDCECE60827.2024.10549556.
X.-T. Nguyen, D.-H. Le, T.-T. Bui, H.-T. Huynh, C.-K. Pham, “A flexible high-bandwidth low-latency multi-port memory controllers,” Vietnam Journal of Science and Technology, vol. 56, no. 3, pp. 357–369, 2018. https://doi.org/10.15625/2525-2518/56/3/11103.
T. Subhashini, M. Kamaraju and K. Babulu, “Design and analysis of multiple port memory architecture for low power applications,” Proceedings of the 2018 Conference on Signal Processing and Communication Engineering Systems (SPACES), Vijayawada, India, 2018, pp. 210-214. https://doi.org/10.1109/SPACES.2018.8316348.
K.S. Sikand, L. Zartman, S. Rabiee, J. Biswas, “Robofleet: Open source communication and management for fleets of autonomous robots,” Proceedings of the IEEE/RSJ Int. Conf. on Intelligent Robots and Systems (IROS), Prague, Czech Republic, 2021, pp. 406–412. https://doi.org/10.1109/IROS51168.2021.9635830.
K. Sethi, “Design space exploration of algorithmic multi-port memories in high-performance application-specific accelerators,” arXiv preprint arXiv:2007.09363, 2020. [Online]. Available at: https://doi.org/10.48550/arXiv.2007.09363.
M. Vegni, V. Loscrí, C.T. Calafate, P. Manzoni, “Communication technologies enabling effective UAV networks: A standards perspective,” IEEE Communications Standards Magazine, vol. 5, no. 4, pp. 33–40, 2021. https://doi.org/10.1109/MCOMSTD.0001.2000074.
E. Pereira, L. Luza, N. Moura, L. Ost, N. Calazans, F. Moraes, R. Garibotti, “Assessment of communication protocols’ latency in co-processing robotic systems,” Proceedings of the 2023 21st IEEE Interregional NEWCAS Conference (NEWCAS), 2023, pp. 1–5. https://doi.org/10.1109/NEWCAS57931.2023.10198085.
R. Siegwart, I.R. Nourbakhsh, D. Scaramuzza, Introduction to Autonomous Mobile Robots, MIT Press, 2011, 472 p.
X. Wang, C. Yuen, S.H. Dau, “Delay minimization for network coded cooperative data exchange with rate adaptation,” Proceedings of the 2013 IEEE 78th Vehicular Technology Conference (VTC Fall), Las Vegas, NV, USA, 2013, pp. 1–5. https://doi.org/10.1109/VTCFall.2013.6692154.
N. Koul, N. Kumar, A. Sayeed, C. Verma, M.S. Raboaca, “Data exchange techniques for Internet of Robotic Things: Recent developments,” IEEE Access, vol. 10, pp. 102087–102106, 2022. https://doi.org/10.1109/ACCESS.2022.3209376.
I.I. Ivanov, Element base of electronic device, Kyiv: Tekhnika, 2020, 320 p. (in Ukrainian).
W. Wolf, FPGA-Based System Design, Upper Saddle River, NJ: Prentice Hall, 2004.
B.A. Demyda, Yu.M. Rashkevych, I.H. Tsmots, Multi-port memory, Patent of Ukraine No. 23358, 1998, Bulletin no. 4. (in Ukrainian).
Y. Zheng, et al., “Wavelet transform cluster analysis of UAV images for sustainable development of smart regions due to inspecting transport infrastructure,” Sunstainability, vol. 17, issue 3, 927, 2025. https://doi.org/10.3390/su17030927.
W. Huan, et al., “Haar wavelet-based classification method for visual information processing systems,” Applied Sciences, vol. 13, issue 9, 5515, 2023. https://doi.org/10.3390/app13095515.
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